The architectural register set or register space of a processor is typically physically integrated within the processor (i.e., is on-chip). Register space or registers may be used to facilitate the rapid execution of instructions and manipulation of operand values by a processor. As is well known, the registers making up a register space are not a shared resource and, as a result, can be accessed more rapidly than other resources that are physically external or separate from the processor chip (i.e., off-chip) and/or which are shared with other agent resources. The register space of a processor is not subject to memory coherency schemes (such as those that are used within multiprocessor systems) and other operational overhead associated with the management of shared memory resources. Also, using a memory stack in lieu of a larger register file introduces additional overhead associated with address calculations.
Some microprocessors or processors provide a relatively limited register space or architectural register set. For example, the thirty-two bit Intel processor families, which are collectively referred to as IA-32 processors, provide eight thirty-two bit general purpose registers, which are located on-chip. Unfortunately, many compiler optimizations, which are usually used to increase the effective instruction-per-clock-cycle (IPC) rate of processors, typically require more than eight general purpose registers. Additionally, a larger number of registers is generally beneficial because a larger number of registers enables program execution to be carried out using fewer memory-based operations, thereby reducing the overhead associated with accessing stack-based operands and, thus, reducing cache occupation and bandwidth (i.e., cache ports) overhead. Reducing the number of stack-based memory operations performed by a processor can free a substantial amount of cache space and bandwidth for use by other load, store and prefetch instructions, which can substantially increase the IPC rate of the processor.
While it is a relatively simple matter to redesign a processor to have a larger register space, such a processor redesign typically requires changes to the instruction set encodings to enable the redesigned processor to efficiently use the additional register space. Furthermore, instruction set encoding changes are typically not backward compatible with earlier versions of the processor that have a smaller register space.